CADENCE EDA Workshop: From Schematic to GDSII File Generation 2019, Thiagarajar College of Engineering, Madurai, Tamil Nadu, 11th - 12th October 2019

Registrations Closed
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Event Type:
Venue/Offline Mode
Start Date :
11th October 2019
End Date :
12th October 2019
Location :
Madurai, Tamil Nadu
Organizer :
Thiagarajar College of Engineering
Category :
Workshop
CADENCE EDA Workshop: From Schematic to GDSII File Generation 2019

About Event

The aim of this workshop is to provide hands-on experience on the state -of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).

Events

Workshop Topics
 Digital Design and Sign-off (Verilog/VHDL)
 Specifications
 Run Conformal Equivalence Checks
 Digital Implementation
 Synthesis and Test
 ASIC Physical Design
 Custom IC/Analog/RF Design
 Schematic Design with Virtuoso
 Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator Layout
 Assura Physical Verification - DRC/LVS
 Assura ParasticsExtraction
 Post Layout Simulation
 Generation of GDSII file
Benefits
 Concepts driven learning with application orientation
 Opportunity to work on industry standard design case studies
 Better preparedness to pursue final year mini/major project
 Excellent Career Oppournities in emerging Technologies- RFIC for IoT, Biomedical Applications and 5G communications

Workshops

Workshop Topics
 Digital Design and Sign-off (Verilog/VHDL)
 Specifications
 Run Conformal Equivalence Checks
 Digital Implementation
 Synthesis and Test
 ASIC Physical Design
 Custom IC/Analog/RF Design
 Schematic Design with Virtuoso
 Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator Layout
 Assura Physical Verification - DRC/LVS
 Assura ParasticsExtraction
 Post Layout Simulation
 Generation of GDSII file
Benefits
 Concepts driven learning with application orientation
 Opportunity to work on industry standard design case studies
 Better preparedness to pursue final year mini/major project
 Excellent Career Oppournities in emerging Technologies- RFIC for IoT, Biomedical Applications and 5G communications

Departments:

CSE ECE EEE Design

How to reach Thiagarajar College of Engineering, Madurai

Dept. of Electronics and Communication Engg.
Thiagarajar College of Engineering
Madurai - 625 015

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CADENCE EDA Workshop: From Schematic to GDSII File Generation 2019 Thiagarajar College of Engineering Madurai Tamil Nadu October 2019 Workshops Workshops in Madurai Workshops in Tamil Nadu

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